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8-bit single chip microcomputers gms810 series user`s manual ? gms81004 ? gms81008 ? gms81016 ? GMS81024 ? gms81032
revision 3.0 published by mc u application team in hyundai elcetronics co., ltd. ? h y undai electronics co., ltd. 1998 all right reserved. additional information of this manual may be served by hyundai electionics offices in korea or distributors and representative listed at address directory. h yundai electionics reserves the right to make changes to any information here in at any time without notice. the information, diagrams, and other data in this manual are correct and reliable; however, hyundai electionics co., ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
table of contents table of contents chapter 1 overview 1.1 features & pin assignments . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 port structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 1-10 chapter 2 function description 2.1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 tcall vector area . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 zero-page peripheral registers . . . . . . . . . . . . . . . . . . . 2-8 chapter 3 i/o port 3.1 port r0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 port r1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 port r2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 chapter 4 peripheral hardware 4.1 clock generating circuit . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
table of contents chapter 5 interrupt 5.1 interrupt source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3 interrupt accept mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 interrupt processing sequence . . . . . . . . . . . . . . . . . . . . 5-7 5.5 software interrupt . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.6 multiple interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.7 key scan input processing . . . . . . . . . . . . . . . . . . . . . . . 5-11 chapter 6 standby function 6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 standby mode release . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 release operation of standby mode . . . . . . . . . . . . . . . 6-5 chapter 7 reset function 7.1 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 low voltage detection mode . . . . . . . . . . . . . . . . . . . . . 7-4 appendix instruction set table programmer`s guide mask option list
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
1 - 1 chapter 1. overview chapter 1. overview the gms810 series is the high speed and low voltage operating 8-bit single chip microcomputers. this mcu contains g8mc core, rom, ram, input/output ports and five multi-function timer/counters. 1.1 features & pin assignments (top view) ? rom size . . . . . . . . . . . . . 4,096 bytes ( gms81004 ) , 8,192 bytes (gms81008 ) . . . . . . . . . . . . . 16,384 bytes ( gms81016 ) ,24,576 bytes(GMS81024 ) . . . . . . . . . . . . . 32,768 bytes ( gms81032 ) ? ram size . . . . . . . . . . . . . 448 bytes ? instruction execution time . . 1us @xin=4mhz ? timer ? timer/counter . . . . . . 8bit * 2ch , 16bit * 1ch ? basic interval time . . . 8bit * 1ch ? watch dog timer . . . . 6bit * 1ch ? power on reset ? power saving operation modes ? stop ? 8 interrupt sources ? nested interrupt control is available ? operating voltage ? 2.0~4.0v @2mhz ? 2.2~4.0v @4mhz ? low voltage detection circuit ? watch dog timer auto start ( during 1second after power on reset ) ? package ? 20sop/20pdip/24sop/24skinny dip/28sop/28skinny dip ? 44plcc ? i/o port 20pin 24pin 28pin 44pin input 3 3 3 3 output 2 2 2 2 i/o 13 17 21 24
1 - 2 chapter 1. overview pin assignment r11 r10 vdd xout xin r00 r01 r02 r03 r20 1 2 3 4 5 7 8 9 10 6 r16 r17 remout reset test r07 r06 r05 r04 vss 20 19 18 17 16 15 14 13 12 11 r13 r12 r11 r10 vdd xout xin r00 r01 r02 r03 r20 1 2 3 4 5 7 8 9 10 11 12 6 r14 r15 r16 r17 remout reset test r07 r06 r05 r04 vss 24 23 22 21 20 19 18 17 16 15 14 13 r14 r15 r16 r17 remout reset test r07 r06 r05 r04 vss r24 r23 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r13 r12 r11 r10 vdd xout xin r00 r01 r02 r03 r20 r21 r22 1 2 3 4 5 7 8 9 10 11 12 13 14 6 28pin r27 vss remout reset test r07 r06 r05 39 38 37 36 35 34 33 32 31 30 29 44plcc r25 r26 7 8 9 10 11 12 13 14 vdd xout xin r00 r01 r02 15 16 17 r13 r12 r11 r10 6 5 4 3 2 1 44 43 42 41 40 r14 r15 r16 r17 r22 r21 r20 r03 18 19 20 21 22 23 24 25 26 27 28 r23 r24 vss r04 nc nc nc nc nc nc nc nc nc nc nc nc 24pin 24pin 20pin
1 - 3 1.2 block diagram ` g8mc core ram (448byte) rom (16k byte) watchdog timer timer interrupt key scan int. generation block clock gen. / system control prescaler / b.i.t r0 port r1 port r2 port vdd vss xout xin reset test r10~r17 r00~r07 r11/int1 r12/int2 remout r17/t0 r16/t1 r15/t2 r14/ec r00~r07 r10~r17 r20~r27 chapter 1. overview
1 - 4 1.3 package dimension chapter 1. overview 1.3.1 20sop pin dimension(dimensions in inch) 1.3.2 20pdip pin dimension (dimensions in inch)
1 - 5 chapter 1. overview 1.3.3 24sop pin dimension (dimensions in inch) 1.3.4 24skinnydip pin dimension (dimensions in inch)
1 - 6 chapter 1. overview 1.3.5 28sop pin dimension (dimensions in inch) 1.3.6 28skinnydip pin dimension (dimensions in inch)
1 - 7 1.3.7 44plcc pin dimension (dimensions in mm) chapter 1. overview
1 - 8 1.4 pin function pin name input/ output function @ reset @ stop r00 i/o input state of before stop r01 r02 r03 r04 r05 r06 r07 r10 r11/int1 r12/int2 r13 r14/ec r15/t2 r16/t1 r17/t0 r20 r21 r22 r23 r24 xin xout remout reset test vdd vss i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i o o i i p p - each bit of the port can be individually configured as an input or an output by user software - push-pull output - cmos input with pull-up resistor (option) - can be programmable as key scan input - pull-ups are automatically disabled at output mode input state of before stop - cmos input with pull-up resistor (option) - push-pull output - can be programmable as key scan input or open drain output - direct driving of led(n-tr) - pull-ups are disabled at output mode input state of before stop - cmos input with pull-up resistor (option) - push-pull output - direct driving of led(n-tr) - pull-ups are disabled at output mode low high - oscillator input - oscillator output `l` output `l` output - high current output `l` level state of before stop - includes pull-up resistor - includes pull-up resistor - positive power supply - ground chapter 1. overview input 20pin 24pin 28pin 44pin 6 8 8 11 7 9 9 15 8 10 10 16 9 11 11 19 12 14 18 27 13 15 19 30 14 16 20 31 15 17 21 32 2 4 4 5 1 3 3 4 - 2 2 3 - 1 1 2 - 24 28 44 - 23 27 43 20 22 26 42 19 21 25 41 r25 i/o r26 i/o r27 i/o 10 12 12 20 - - 13 21 - - 14 22 - - 15 24 - - 16 25 - - - 13 - - - 14 - - - 36 vss p 5 7 7 10 4 6 6 9 18 20 24 38 17 19 23 37 16 18 22 33 3 5 5 8 11 13 17 26 - - - 35
1 - 9 1.5 port structure 1.5.1 r0 port chapter 1. overview r00 r01 r02 r03 r04 r05 r06 r07 pin @ reset hi - z or high-input (with pullup) mux data reg direction reg data bus ? rd circuit type vdd vss pull-up option pad vdd data bus ? rd
1 - 10 1.5.2 r1 port chapter 1. overview mux data reg direction reg data bus r10 r11/int1 r12/int2 r13 r14/ec pin circuit type @ reset hi - z or high-input (with pullup) vdd vss pull-up option pad vdd t0 r11...int1 t0 r12...int2 t0 r14...ec rd open drain selection mux data reg direction reg data bus r15 / t2 r16 / t1 r17 / t0 hi - z or high-input (with pullup) vdd vss pull-up option pad vdd rd open drain selection mux from r15...t2 from r16...t1 from r17...t0
1 - 11 1.5.3 r2 port chapter 1. overview remout port internal signal remout pin circuit type @ reset low level vdd vss pad mux data reg direction reg data bus r20 r21 r22 r23 r24 r25 r26 r27 pin circuit type @ reset hi - z or high-input (with pullup) vdd vss pull-up option pad vdd ? rd
1 - 12 1.5.4 miscellaneous ports chapter 1. overview pin circuit type @ reset reset low level vss pad vdd vss from power on reset circuit pull-up resistor test high level pad vdd vss pull-up resistor xin xout oscillation xin xout vss from stop circuit
1 - 13 1.6 electrical characteristics 1.6.1 absolute maximum ratings (ta = 25 ? ) chapter 1. overview 1.6.2 recommended operating ranges parameter supply voltage input voltage output voltage operating temperature storage temperature power dissipation symbol vdd vi vo topr tstg pd ratings -0.3 ~ +7.0 -0.3 ~ vdd + 0.3 0 ~ 70 -65 ~ 150 700 -0.3 ~ vdd + 0.3 unit v v ? ? mw v parameter symbol condition unit supply voltage vdd1 vdd2 operating temperature topr oscillation frequency fxin fxin = 1mhz fxin = 2mhz fxin = 4mhz min. typ. max. v v mhz ? 2.0 2.2 4.0 4.0 2.0 1.0 0 70 4.0 1.6.2 recommended operating ranges
1 - 14 1.6.3 dc characteristics (vdd = 2.0~4.0, vss = 0v, ta = 0 ? ~ 70 ? ) chapter 1. overview parameter symbol condition specification unit max typ min v dd 0.8v dd high level input voltage v ih 1 r11, r12, r14, resetb v ih 2 v v v dd 0.7v dd r0, r1(except r11,r12,r14 ) , r2 v il 1 r11, r12, r14, resetb v il 2 r0, r1(except r11,r12,r14 ) , r2 low level input voltage 0.2v dd 0 0.3v dd 0 v v high level input leakage current low level input leakage current i ih i il v oh 1 v oh 2 v oh 3 v ol 1 v ol 2 high level output voltage low level output voltage high level output leakage current low level output leakage current i ohl i oll i p 1 resetb i p 2 r0, r1, r2 input pull-up current 60 30 15 40 20 10 ua ua 10 4 6 2.4 ma 6 2.4 3 1.2 10 3 --- 8 2 --- power supply current i dd operating current f xin =4mhz i stop stop mode current oscillator stop r0,r1,r2,resetb r0,r1,r2,resetb (without pull-up) r0 r1(exceptr17),r2 r17 r0 r1, r2 r0, r1, r2 r0, r1, r2 v ih =v dd v il =0v i oh =-0.5ma i oh =-1ma i oh =-8ma i ol =1ma i ol =5ma v oh =v dd v ol =0v v dd =3v v dd =3v f xin =2mhz v dd =4v v dd =2.2v v dd =4v v dd =2v v dd =4v v dd =2v 1 -1 ua ua v dd -0.4 v dd -0.4 v dd -0.9 v v v 0.4 0.8 v v 1 -1 ua ua ma ma ma ua ua i ol remout v ol =1v 0.5 - 3 ma i oh remout v oh =2v -30 -12 -5 ma ram retention supply voltage v ret 0.7 v high level output current low level output current v oh 5 osc i oh =-200ua v dd -0.9 v v ol 5 osc i ol =200ua 0.8 v
1 - 15 ? gms810 series remout port i oh characteristics graph ? gms810 series remout port i ol characteristics graph chapter 1. overview -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0 1 2 3 4 voh(v) ioh(ma) vdd=4v vdd=3v vdd=2v 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 0 1 2 3 4 vol(v) iol(ma) vdd=4v vdd=3v vdd=2v
1 - 16 1.6.4 ac characteristics (vdd = 2.0~4.0, vss = 0v, ta = 0 ? ~ 70 ? ) chapter 1. overview no parameter symbol unit pin specification min typ max external clock input cycle time system clock cycle time external clock pulse width high external clock pulse width low external clock rising time external clock falling time interrupt pulse width high interrupt pulse width low tcp ns xin 250 500 1000 1 2 3 4 5 6 7 8 reset input pulse width low 9 tsys tcph tcpl trcp tfcp tih til trstl ns ns ns ns ns tsys tsys tsys xin xin xin xin int1~int2 reset int1~int2 500 1000 2000 40 40 40 40 2 2 8 event counter input pulse width high 10 event counter input pulse width low 11 event counter input pulse rising time 12 event counter input pulse falling time 13 tech tecl trec tfec tsys tsys ns ns ec ec ec ec 2 2 40 40 * refer to fig 1-1
1 - 17 chapter 1. overview reset trstl 0.2vcc ec tech tecl 0.8vcc 0.8vcc 0.2vcc trec tfec tih int1 int2 til 0.8vcc 0.2vcc tcp tcph xin tcpl trcp tfcp vcc-0.5v 0.5v * fig-1 : clock, int, reset. ec input timing
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
2 - 1 chapter 2. function description 2.1 registers pch pcl a x y sp psw n v g b h i z c ? 15 7 0 7 0 15 7 0 7 0 7 0 7 0 7 0 ? carry flag zero flag interrupt enable flag half carry flag break flag g flag overflow flag negative flag program status word stack pointer ?? 1 y-register x-register ya (16bit accumulator) a-register program counter pch pcl 15 7 0 fixed as 01 xx h (=ram 1page) ? ? sp ?? 1 stack address chapter 2. function description
2 - 2 chapter 2. function description 2.1.1 a register - 8bit accumulator. - in the case of 16-bit operation, compose the lower 8-bit of a, upper 8bit in y (16-bit accumulator) - in the case of multiplication instruction, execute as a multiplier register. after multiplication operation, the lower 8-bit of the result enters. (y*a ?? ya) - in the case of division instruction, execute as the lower 8-bit of dividend. after division operation, quotient enters. 2.1.2 x register - general-purpose 8-bit register - in the case of index addressing mode within direct page(ram area), execute as index register. - in the case of division instruction, execute as register. 2.1.3 y register - general-purpose 8-bit register - in the case of index addressing mode, execute as index register - in the case of 16-bit operation instruction, execute as the upper 8-bit of ya (16-bit accumulator). - in the case of multiplication instruction, execute as a multiplicand register. after multiplication operation, the upper 8-bit of the result enters. - in the case of division instruction, execute as the upper 8-bit of dividend. after division operation, remains enters. - can be used as loop counter of conditional branch command. (e.g.dbne y, rel) 2.1.4 stack pointer - in the cases of subroutine call, interrupt and push, pop, reti, ret instruction, stack data on ram or in the case of returning, assign the storage location having stacked data. - stack area is constrained within 1-page (00h-ffh). the sp is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted; and the sp is pre-incremented when a return or a pop instruction is executed. - sp should be initialized as follows ex) ldx #0feh : 0feh ?? x reg. txsp : x reg. ?? sp - the behaviors of stack pointer according to each instruction are the following.
2 - 3 chapter 2. function description 2.1.4.1 interrupt m(sp) ?? (pch) sp ?? sp - 1 m(sp) ?? (pcl) sp ?? sp - 1 m(sp) ?? (psw) sp ?? sp - 1 2.1.4.2 reti( return from interrupt ) sp ?? sp + 1 (psw) ?? m(sp) sp ?? sp + 1 (pcl) ?? m(sp) sp ?? sp + 1 (pch) ?? m(sp) 2.1.4.3 subroutine call m(sp) ?? (pch) sp ?? sp - 1 m(sp) ?? (pcl) sp ?? sp - 1 2.1.4.4 ret(return from subroutine) sp ?? sp + 1 (pcl) ?? m(sp) sp ?? sp + 1 (pch) ?? m(sp)
2 - 4 2.1.4.5 push a(x, y, psw) m(sp) ?? a sp ?? sp - 1 2.1.4.6 pop a(x, y, psw) sp ?? sp + 1 a ?? m(sp) 2.1.5 pc (program counter) - program counter is a 16-bit counter consisted of 8-bit register pch and pcl. - addressing space is 64k bytes. 2.1.6 psw (program status word) - psw is an 8-bit register. - consisted of the flags showing the post state of operation and the flags determining the cpu operation, initialized as 00h in reset state. 2.1.7 flag register . 2.1.7.1 carry flag (c) - after operation, set when there is a carry from bit7 of alu or there is not a borrow. - set by setc and clear by clrc. - executable as 1-bit accumulator. - branch condition flag of bcs, bcc. 2.1.7.2 zero flag (z) - after operation also including 16-bit operatiion, set if the result is ? 0 ? - branch condition flag of beq, bne. 2.1.7.3 interrupt enable flag (i) - master enable flag of interrupt except for rst (reset). - set and cleared by ei, di chapter 2. function description
2 - 5 2.1.7.4 half carry flag (h) - after operation, set when there is a carry from bit3 of alu or there is not a borrow from bit4 of alu. - can not be set by any instruction. - cleared by clrv instruction like v flag. 2.1.7.5 break flag (b) - set by brk (s/w interrupt) instruction to distinguish brk and tcall instruction having the same vector address. 2.1.7.6 g flag (g) - set and cleared by setg, clrg instruction. - assign direct page (0-page, 1-page). - addressable directly to ram 1-page by setg. and to ram 0-page by clrg. 2.1.7.7 overflow flag (v) - after operation, set when overflow or underflow occurs. - in the case of bit instruction, bit6 memory location is transferred to v-flag. - cleared by clrv instruction, but not set by any instruction. - branch condition flag of bvs, bvc. 2.1.7.8 negative flag (n) - set whenever the result of a data transfer or operation is negative (bit7 is set to ? 1 ? ). - in the case of bit instruction, bit7 of memory location is transferred to n-flag - n-flag is not affected by clr or set instruction. - branch condition flag of bpl, bmi. chapter 2. function description
2 - 6 2.2 memory map ram (192 bytes) peripheral registers ram (stack) (256 bytes) non-use rom (24,576 bytes) pcall area tcall vector area interrupt vector area 0-page 1-page direct page program rom u-page 0000h 00bfh 0100h 0200h c000h ff00h ffc0h ffe0h ffffh chapter 2. function description rom (8,192 bytes) rom (4,096 bytes) e000h f000h rom (32,768 bytes) 8000h rom (16,384 bytes) a000h gms81004 gms81008 gms81016 gms81032 GMS81024
2 - 7 2.3 tcall vector area tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 ffc0h ffc1h ffc2h ffc3h ffc4h ffc5h ffc6h ffc7h ffc8h ffc9h ffcah ffcbh ffcch ffcdh ffceh ffcfh ffd0h ffd1h ffd2h ffd3h ffd4h ffd5h ffd6h ffd7h ffd8h ffd9h ffdah ffdbh ffdch ffddh ffdeh ffdfh (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) (l) (h) * * this vector area is used in brk command and tcall0 command. chapter 2. function description
2 - 8 2.4 zero-page peripheral registers address 00c0h function registers port r0 data reg. r/w r/w symbol r0 reset value 7 6 5 4 3 2 1 0 undefined 00c1h port r0 data direction reg. w r0dd 00 00c2h port r1 data reg. r/w r1 undefined 00c3h port r1 data direction reg. w r1dd 00 00c4h port r2 data reg. r/w r2 undefined 00c5h port r2 data direction reg. w r2dd 00 00c6h reserved 00c7h clock control reg. w ckctlr basic interval reg. r bitr undefined 00c8h watch dog timer reg. w wdtr 00c9h port r1 mode reg. w pmr1 00 00cah int. mode reg. r/w imod 00cbh ext. int. edge selection w ieds 00 00cch int. enable reg. high r/w ienl 00cdh int. request flag reg. low r/w irql 00ceh int. enable reg. high r/w ienh 00cfh int. request flag reg. high r/w irqh 00d0h timer 0 (16bit) mode reg. r/w tm0 00 00d1h timer 1 (8bit) mode reg. r/w tm1 00 00d2h timer 2 (8bit) mode reg. r/w tm2 00 00d3h timer 0 high-msb data reg. w t0hmd undefined 00d4h timer 0 high-lsb data reg. w t0hld undefined 00d5h timer0 low-msb data reg. w t0lmd undefined timer0 low-msb count reg. r undefined - - 1 1 0 1 1 1 - 0 0 0 1 1 1 1 - - 0 0 0 0 0 0 - 0 0 - - - - - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - - 0 0 - - - - - chapter 2. function description 00d6h timer0 low-lsb data reg. w t0lld undefined timer0 low-lsb count reg. r undefined 00d7h timer 1 high data reg. w t1hd undefined 00d8h timer1 low data reg. w t1ld undefined timer1 low count reg. r undefined 00d9h timer2 data reg. w t2dr undefined timer2 count reg. r undefined 00dah timer 0/ timer1 mode reg. r/w tm01 00 00dbh reserved 00dch standby mode release reg0 w smrr0 00 00ddh standby mode release reg1 w smrr1 00 00deh port r1 open drain assign reg. w r1odc 00 - ; not used * caution : write only register can not be accessed by bit manipulation instruction. : do not access the reserved registers .
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
3 - 1 chapter 3. i/o port chapter 3. i/o ports the gms810series has 21 i/o ports which are port0(8 i/o), port1 (8 i/o) and port2 (8 i/o). each port contains data direction register which controls i/o and data register which stores port data. 3.1 port r0 3.1.1 port r0 registers register r0 i/o data direction register symbol r/w reset value address r0dd w 00h 00c1h r0 data register r0 r/w undefined 00c0h table 3.1 port r0 registers 3.1.2 i/o data direction register (r0dd) r0dd7 r0dd6 r0dd5 r0dd4 r0dd3 r0dd2 r0dd1 r0dd0 <00c1h> r0dd bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w r0 i/o data direction register(r0dd) is 8-bit register, and can assign input state or output state to each bit. if r0dd is ? 1 ? , port r0 is in the output state, and if ? 0 ? , it is in the input state. r0dd is write-only register. since r0dd is initialized as ? 00h ? in reset state, the whole port r0 becomes input state. 3.1.1 data register(r0) r07 r06 r05 r04 r03 r02 r01 r00 <00c0h> r0 bit initial value r/w 7 x r/w 6 x r/w 5 x r/w 4 x r/w 3 x r/w 2 x r/w 1 x r/w 0 x r/w port0 data register (r0) is 8-bit register to store data of port r0. when setted as the output state by r0dd, and data is written in r0, data is outputted into r0 pin. when set as the input state, input state of pin is read. the initial value of r0 is unknown in reset state.
3 - 2 3.2 port r1 pin name r10 r11/int1 r12/int2 r13 r14/ec r15/t2 r16/t1 r17/t0 fig 3.1 pin function of port r1 port selection function selection r10(i/o) r11(i/o) r12(i/o) r13(i/o) r14(i/o) r15(i/o) r16(i/o) r17(i/o) int1 (input) int2 (input) ec (input) t2 (output) t1 (output) t0 (output) register r1 i/o data direction register symbol r/w reset value address r1dd w 00h 00c3h r1 data register r1 r/w undefined 00c2h table 3.1 port r1 registers 3.2.1 port r1 register r1 port mode register pmr1 w 00h 00c9h r1 port open drain assign register r10dc w 00h 00ceh 3.2.2 i/o data direction register (r1dd) r1dd7 r1dd6 r1dd5 r1dd4 r1dd3 r1dd2 r1dd1 r1dd0 <00c3h> r1dd bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w r1 data direction register(r1dd) is 8-bit register, and can assign input state or output state to each bit. if r1dd is ? 1 ? , port r1 is in the output state, and if ? 0 ? , it is in the input state. r1dd is write-only register. since r1dd is initialized as ? 00h ? in reset state, the whole port r1 becomes input state. chapter 3. i/o port
3 - 3 3.2.3 data register(r1) r17od r16od r15od r14od r13od r12od r11od r10od <00deh> r1odc bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w r1 data register(r1) is 8-bit register to store data of port r1. when set as the output state by r1dd, and data is written in r1, data is output into r1 pin. the initial value of r1 is unknown in reset state. r17 r16 r15 r14 r13 r12 r11 r10 <00c2h> r1 bit initial value r/w 7 x r/w 6 x r/w 5 x r/w 4 x r/w 3 x r/w 2 x r/w 1 x r/w 0 x r/w port r1 open drain assign register(r1odc) is 8bit register, and can assign r1 port as open drain output port each bit, if corresponding port is selected as output. if r1odc is selected as ? 1 ? , port r1 is open drain output, and if selected as ? 0 ? , it is push-pull output. r1odc is write-only register and initialized as ? 00h ? in reset state. 3.2.4 port r1 open drain assign register (r1odc) chapter 3. i/o port
3 - 4 t0s t1s t2s ecs - int2s int1s - <00c9h> pmr1 bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w 3.2.5 port r1 mode register (pmr1) r1 port mode register(pmr1) is 8-bit register, and can assign the selection mode for each bit. when set as ? 0 ? , corresponding bit of pmr1 acts as port r1 selection mode, and when set as ? 1 ? , it becomes function selection mode. bit name t0s pmr1 selection mode remarks table 3.3 selection mode of pmr1 0 1 r17 sel(i/o) t0 sel (output) - output port of timer0 t1s 0 1 r16 sel (i/o) t1 sel (output) - output port of timer1 t2s 0 1 r15 sel (i/o) t2 sel (output) - output port of timer2 ecs 0 1 r14 sel (i/o) ec sel (input) - input port of timer0 event input - 0 1 int2s 0 1 r12 sel (i/o) int2 sel (input) - input port of timer0 input capture int1s 0 1 r11 sel (i/o) int1 sel (input) - - - pmr1 is write-only register and initialized as ? 00h ? in reset state. therefore, becomes port selection mode. port r1 can be i/o port by manipulating each r1dd bit, if corresponding pmr1 bit is selected as ? 0 ? . chapter 3. i/o port
3 - 5 3.3 port r2 3.3.1 port r2 registers registers r2 i/o data direction register symbol r/w reset value address r2dd w 00h 00c5h r2 data register r2 r/w undefined 00c4h table 3.3 port r2 registers r2dd7 r2dd6 r2dd5 r2dd4 r2dd3 r2dd2 r2dd1 r2dd0 <00c5h> r2dd bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w 3.3.2 i/o data direction register (r2dd) r2 data direction register(r2dd) is 8-bit register, and can assign input state or output state or output state to each bit. if r2dd is ? 1 ? , port r2 is in the output state, and if ? 0 ? , it is in the input state. r2dd is write-only register. since r2dd is initialized as ? 00h ? in reset state, the whole port r2 becomes input state. r27 r26 r25 r24 r23 r22 r21 r20 <00c4h> r2 bit initial value r/w 7 x r/w 6 x r/w 5 x r/w 4 x r/w 3 x r/w 2 x r/w 1 x r/w 0 x r/w 3.3.3 data register (r2) r2 data register(r2) is 8-bit register to store data of port r2. when setted as the output state by r2dd, and data is written in r2, data is output into r2 pin. when setted as input state, input state of pin is read. the initial value of r2 is unknown in reset state. chapter 3. i/o port
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
4 - 1 chapter 4. peripheral hardware chapter 4. peripheral hardware 4.1 clock generating circuit clock generating circuit consists of clock pulse generator(c.p.g), prescaler, basic interval timer(b.i.t) and watch dog timer. the clock applied to the xin pin divided by two is used as the internal system clock. fig. 4.1 block diagram of clock generating circuit 9 prescaler c.p.g mux wdt (6) comparator internal data bus 0 1 2 3 4 0 5 6 6 wdton to reset circuit ifwdt wdtcl ifbit 5 0 7 0 fcpu fex ps1 enpck peripheral ckctlr btcl 3 8 osc circuit b.i.t (8) 6 wdtr internal system clock 5
4 - 2 4.1.1 oscillation circuit oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator. as shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between xout and xin. clock from oscillation circuit makes cpu clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. alternately, the oscillator may be driven from an external source as shown is fig. 4.2.- (b). in the standby(stop) mode, oscillatiion stop, xout state goes to ? high ? , xin state goes to ? low ? , and built-in feed back resistor is disabled. (a) external crystal (ceramic) oscillator circuit cout cin xin xout (b) external clock input circuit xin xout external clock fig. 4.2 oscillator configurations chapter 4. peripheral hardware frequency resonator maker part name load capacitor operating voltage *. recommendable resonator 4.0mhz ?? mc type is building in load capacitior.ccr type is chip type. zta4.00mg cin=cout=30pf 2.2 ~ 4.0v fcr4.0mc5 cin=cout=open 2.2 ~ 4.0v cq tdk fcr4.0m5 cin=cout=33pf 2.2 ~ 4.0v tdk ccr4.0mc3 cin=cout=open 2.2 ~ 4.0v tdk kbr- 4.0mkc cin=cout=open 2.2 ~ 4.0v kyocera kbr- 4.0msb cin=cout=33pf 2.2 ~ 4.0v kyocera
4 - 3 4.1.2 prescaler prescaler consists of 12-bit binary counter. the clock supplied from oscillation circuit is input to prescaler (fex). the divided output from each bit of prescaler is provided to peripheral hardware. 4.1.3 peripheral hardware clock control clock to peripheral hardware can be stopped by bit4 (enpck) of ckctlr register. enpck is set to ? 1 ? in reset state. ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 b.i.t peripheral ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 fex enpck fcpu fex(mhz) freq period(s) 4 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 ps0 2m 1m 500k 250k 125k 62.5k 31.25k 15.63k 7.183k 3.906k 1.953k 0.976k 4m 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u 512u 1024u 250n freq period(s) 2 1m 500k 250k 125k 62.5k 31.25k 15.63k 7.183k 3.906k 1.953k 0.976k 2m 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u 512u 1024u 0.488k 2048u fig. 4.3 block diagram of prescaler chapter 4. peripheral hardware
4 - 4 - - wdton enpck btcl bts2 bts1 bts0 ckctlr w <00c7h> enpck 0 1 peripheral clock stopped provided 7 0 clock control register 4.1.4 basic interval timer (b.i.t) - 8bit binary counter - use the bit output of prescaler as input to secure the oscillation stabilization time after power-on - secures the oscillation stabilization time in standby mode (stop mode) release - contents of b.i.t can be read - provides the clock for watch dog timer. - - wton enpck btcl bts2 bts1 bts0 mux bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ckctlr bitr ifbit ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 data bus fig. 4.4 block diagram of basic interval timer chapter 4. peripheral hardware data bus
4 - 5 4.1.4.1 control of b.i.t if bit3(btcl) of ckctlr is set to ? 1 ? , b.i.t is cleared, and then, after one machine cycle, btcl becomes ? 0 ? , and b.i.t starts counting. btcl is set to ? 0 ? in reset state. - - wdton enpck btcl bts2 bts1 bts0 ckctlr w <00c7h> btcl 0 1 b.i.t operation free-run automatically cleared, after one cycle 7 0 clock control register 4.1.4.2 input clock selection of basic interval timer the input clock of b.i.t can be selected from the prescaler within a range of 2us to 256us by clock input selection bits(bts2~bts0). (at fex = 4mhz). in reset state, or power on reset, bts2=1, bts1=1, bts0=1 to secure the longest oscillation stabilization time. b.i.t can generate the wide range of basic interval time interrupt request(ifbit) by selecting prescaler output. interrupt interval can be selected to 8 kinds of interval time as shown in table. 4.1. chapter 4. peripheral hardware
4 - 6 - - wdton enpck btcl bts2 bts1 bts0 ckctlr w <00c7h> bts2 0 0 7 0 4.1.4.3 reading basic interval timer by reading of the basic interval timer register(bitr), we can read counter value of b.i.t. because b.i.t can be cleared or read, the spending time up to maximum 65.5ms can be available. b.i.t is read-only register. if b.i.t register is written, then ckctlr register with same address is written. bts1 0 0 bts0 0 1 b.i.t. input clock ps3 (2 u s) ps4 (4 u s) standby release time 512 u s 1,024 u s 0 0 1 1 0 1 ps5 (8 u s) ps6 (16 u s) 2,048 u s 4,096 u s 1 1 0 0 0 1 ps7 (32 u s) ps8 (64 u s) 8,192 u s 16,384 u s 1 1 1 1 0 1 ps9 (128 u s) ps10 (256 u s) 32,768 u s 65,536 u s table 4.1 standby release time according to bts bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bitr r <00c7h> 7 0 basic interval timer register chapter 4. peripheral hardware
4 - 7 4.1.5 watch dog timer watch dog timer(wdt) consists of 6-bit binary counter, 6-bit comparator, and watch dog timer register (wdtr). wdt0 wdt1 wdt2 wdt3 wdt4 wdt5 ifbit 0 5 6bit comparator wdtr 0 6 wdtr0 wdtr1 wdtr2 wdtr3 wdtr4 wdtr5 wdtcl w <00c8h> if wdt clr wdton to reset circuit fig. 4.5 block diagram of watch dog timer 4.1.5.1 control of wdt watch dog timer can be used 6-bit general timer or specific watch dog timer by setting bit5(wdton) of clock control register(ckctlr). - - wdton enpck btcl bts2 bts1 bts0 ckctlr w <00c7h> wdton 0 1 watch dog timer function control 6-bit timer watch dog timer 7 0 clock control register internal data bus chapter 4. peripheral hardware
4 - 8 by assigning bit6(wdtcl) of wdtr, 6-bit counter can be cleared - wdtcl wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 wdtr w <00c8h> wdtcl 0 1 watch dog timer operation free-run automatically cleared, after one machine cycle 7 0 watch dog timer register determine interval of ifwdt interval of ifwdt = value of wdtr ?? interval of ifbit (caution) : after wdtcl = 1, timer maximum error is one cycle of ifbit. 4.1.5.2 wdt interrupt interval wdt interrupt(ifwdt) interval is determined by the interrupt ifbit interval of basic interval timer and the value of wdt register. interval of ifwdt = (ifbit interval) * (wdtr value) interval of ifwdt : 512us ?? 1 = 512us (min>) : 65,536us ?? 63 = 4,128,768us (max>) as ifbit (basic interval timer interrupt request) is used for input clock of wdt, input clock cycle is possible from 512us to 65,536us by bts. (at fex = 4mhz) *at hardware reset time ,wdt starts automatically.therefore, the user must select the ckctlr,wdtr before wdt overflow. ( reset wdtr value = 0fh,15 interval of wdt = 65,536 ?? 15 = 983040 us (about 1second ) ) chapter 4. peripheral hardware
4 - 9 - - wdton enpck btcl bts2 bts1 bts0 ckctlr w <00c7h> bts2 0 0 7 0 bts1 0 0 bts0 0 1 input clock of wdt max. interval of wdt output (*note1) 32,756 u s 64,512 u s 0 0 1 1 0 1 129,024 u s 258,048 u s 1 1 0 0 0 1 516,096 u s 1,032,192 u s 1 1 1 1 0 1 2,064,384 u s 4,128,768 u s *note1) when wdtr register value is 63(3fh) caution : do not use ? 0 ? for wdtr register value. device come into the reset state by wdt 512 u s 1,024 u s 2,048 u s 4,096 u s 8,192 u s 16,384 u s 32,768 u s 65,536 u s chapter 4. peripheral hardware
4 - 10 4.2 timer 4.2.1 timer operation mode timer consists of 16bit binary counter timer0(t0), 8bit binary timer1(t1), timer2(t2), timer data register, timer mode register (tm01, tm0, tm1, tm2) and control circuit. timer data register consists of timer0 high-msb data register(t0hmd), timer0 high- lsb data register(t0hld), timer0 low-msb data register(t0lmd), timer0 low-lsb data register(t0lld), timer1 high data register(t1hd), timer1 low data register(t1ld), timer2 data register(t2dr). any of the ps0~ps5, ps11 and external event input ec can be selected as clock source for t0. any of the ps0~ps3, ps7~ps10 can be selected as clock t1. any of the ps5~ps12 can be selected as clock source for t2. timer0 - 16-bit interval timer - 16-bit event counter - 16-bit input capture - 16-bit rectangular-wave output timer1 - 8-bit interval timer -8-bit rectangular-wave output timer2 - 8-bit interval timer -8-bit rectangular-wave output - modulo-n mode - single/modulo-n mode - timer output initial value setting - timer0~timer1 combination logic output - one interrupt generating every 2nd counter overflow chapter 4. peripheral hardware *relevant port mode register (pmr1 : 00c9h) value should be assigned for event counter, rectangular-wave output and input capture mode.
4 - 11 timer0 (16 bit) polarity selection t0hmd t0hld t0lmd t0lld tout logic t1 hd t1 ld timer1 (8 bit) t2dr timer2 (8 bit) edge selection t2 out/r15 t1 out/r16 remout t0 out/r17 ec/r14 int2/r12 (capture signal) 16 8 8 8 8 8 8 fig. 4.6 timer/counter block diagram chapter 4. peripheral hardware 16
4 - 12 4.2.2 function of timer & counter 16bit timer (t0) 8bit timer (t1) 8bit timer (t2) resolution (ck) max.count resolution (ck) max.count resolution (ck) max.count ps0 ( 0.25us) 16,384us ps0 (0,.25us) 64us ps5 ( 8us) 2.048us ps1 ( 0. 5us) 32,768us ps1 ( 0,5us) 128us ps6 ( 16us) 4,096us ps2 ( 1us) 65,536us ps2 ( 1us) 256us ps7 ( 32us) 8,192us ps3 ( 2us) 131,072us ps3 ( 2us) 512us ps8 ( 64us) 16,384us ps4 ( 4us) 262,144us ps7 ( 32us) 8,192us ps9 ( 128us) 32,768us ps5 ( 8us) 524,288us ps8 ( 64us) 16,384us ps10 ( 256us) 65,536us ps11 (512us) 33,554,432us ps9 ( 128us) 32,768us ps11 ( 512us) 131,072us ec - ps10 (256us) 65,536us ps12 (1,024us) 262,144us fex = 4mhz chapter 4. peripheral hardware
4 - 13 internal data bus 7 6 5 4 3 2 1 0 timer0 h count reg timer0 l count reg timer0 hm data reg timer0 hl data reg timer0 lm data reg timer0 ll data reg single/ modulo-n selection mux ck t0 counter (16 bit) clear ps0 ps1 ps2 ps3 ps4 ps5 ps11 ec m u x d e l a y edge selection mux int. gen. output gen. tm0 r/w <00d0h> <00d5h> <00d6h> <00d3h> <00d4h> <00d5h> <00d6h> 16 16 16 int2 t0int t0 out ift0 fig. 4.7 block diagram of timer0 chapter 4. peripheral hardware data read
4 - 14 tm0 r/w <00d0h> 7 0 t0sl2 t0sl1 t0sl0 input clock sel. notes 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ps0 (250ns) ps1 (500ns) ps2 ( 1us) ps3 ( 2us) ps4 ( 4us) ps5 ( 8us) ps11 (512us) ec * event counter t0ifs timer0 interrupt sel. 0 1 interrupt every counter overflow interrupt every 2nd counter overflow cap0 t0st t0cn t0mod t0ifs t0sl2 t0sl1 t0sl0 t0mod timer0 single / modulo-n sel. 0 1 modulo-n single mode t0cn timer0 counter continuation / pause control 0 1 count pause count continuation t0st timer0 start/stop control 0 1 timer0 stop timer0 start after clear cap0 timer0 interrupt sel. 0 1 timer/counter input capture* *ps1 : not supporting input capture. chapter 4. peripheral hardware timer0 mode register
4 - 15 internal data bus 7 6 5 4 3 2 1 0 timer1 count reg timer1 h data reg timer1 l data reg single/ modulo-n selection mux ck t1 counter (8 bit) ps0 ps1 ps2 ps3 ps7 ps8 ps9 ps10 int. gen. output gen. tm1 r/w <00d1h> <00d7h> <00d8h> t1out ift1 fig. 4.8 block diagram of timer1 output gen. x <00d8h> t1int chapter 4. peripheral hardware
4 - 16 tm1 r/w <00d1h> 7 0 t1sl2 t1sl1 t1sl0 input clock sel. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ps0 (250ns) ps1 (500ns) ps2 ( 1us) ps3 ( 2us) ps7 ( 32us) ps8 ( 64us) ps9 (128us) ps10 (256us) t1ifs timer1 interrupt sel. 0 1 interrupt every counter overflow interrupt every 2nd counter overflow t1st t1cn t1mod t1ifs - t1sl2 t1sl1 t1sl0 t1mod timer1 single / modulo-n sel. 0 1 modulo-n single mode t1cn timer1 countern continuation / pause control 0 1 count pause count continuation timer1 mode register t1st timer1 start/stop control 0 1 timer1 stop timer1 start after clear chapter 4. peripheral hardware
4 - 17 tm01 r/w <00dah> 7 0 t0ut1 t0ut0 tout logic 0 0 1 1 0 1 0 1 and of t0 output and t1 output nand of t0 output and t1 output or of t0 output and t1 output nor of t0 output and t1 output t1init timer1 output initial value 0 1 timer1 output low timer1 output high touts toutb - t0outp t0init t1init tout1 tpit0 t0init timer0 output initial value 0 1 timer0 output low timer0 output high t0outp t0outpolarity selection 0 1 t0out polarity equal to tout logic input signal t0out polarity reverse to tout logic input signal toutb remout port bit control 0 1 remout output low remout output high touts remout port output selection (tout logic or toutb) 0 1 bit(toutb) output through remout tout logic output through remout timer0/timer1 mode register chapter 4. peripheral hardware
4 - 18 internal data bus 7 6 5 4 3 2 1 0 timer2 count reg mux ck t2 counter (8 bit) ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 output gen. tm2 r/w <00d2h> <00d9h> t2 out fig. 4.9 block diagram of timer2 <00d9h> timer2 data reg ift2 chapter 4. peripheral hardware
4 - 19 tm2 r/w <00d2h> 7 0 t2sl2 t2sl1 t2sl0 input clock sel. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ps5 ( 8us) ps6 ( 16us) ps7 ( 32us) ps8 ( 64us) ps9 ( 128us) ps10 ( 256us) ps11 ( 512us) ps12 (1,024us) t2cn timer2 counter continuation / pause control 0 1 count pause count continuation - - - t2st t2cn t2sl2 t2sl1 t2sl0 t2st timer2 start / stop control 0 1 timer2 stop timer2 start after clear chapter 4. peripheral hardware timer2 mode register
4 - 20 pmr1 w <00c9h> 7 0 t0s t1s t2s ecs - int2s int1s - port mode register1 pmr1 t0s port sel. remarks 0 1 - output port of timer0 r17 (i/o) t0 (output) t1s 0 1 - output port of timer1 r16 (i/o) t1 (output) t2s 0 1 - output port of timer2 r15 (i/o) t2 (output) ecs 0 1 - input port of timer0 event r14 (i/o) ec (input) - - - - - - - int2s 0 1 - input port of timer0 input capture r12 (i/o) int2 (input) int1s 0 1 - - r11 (i/o) int1 (input) - - - - - - - ieds w <00cbh> 7 0 - - ied2h ied2l ied1h ied1l - - external interrupt signal edge selectin register ied*h ied*l int* 0 0 1 1 -- fallingedge selection rising edge selection both edge selection 0 1 0 1 chapter 4. peripheral hardware
4 - 21 4.2.3 timer0, timer1 timer0 and timer1 have an up-counter. when value of the up-counter reaches the content of timer data register(tdr), the up-counter is cleared to ? 00h ? , and interrupt(ift0, ift1) is occured at the next clock fig. 4. 10 operatiion of timer0 concurrence concurrence concurrence clear clear clear 0 t0 data registers value t0 value interrupt interrupt interrupt interval period ift0 for timer0, the internal clock(ps) and the external clock(ec) can be selected as counter clock. but timer1 and timer2 use only internal clock. as internal clock. timer0 can be used as internal-timer which period is determined by timer data register(tdr). chosen as external clock, timer0 executes as event-counter. the counter execution of timer0 and timer1 is controlled by t0cn, t0st, cap0, t1cn, t1st, of timer mode register tm0 and tm1. t0cn, t1cn are used to stop and start timer0 and timer1 without clearing the counter. t0st, t1st is used to clear the counter. for clearing and starting the counter, t0st or t1st should be temporarily set to ? 0 ? and then set to ? 1 ? . t0cn, t1cn, t0st and t1st should be set ? 1 ? , when timer counting-up. controlling of cap0 enables timer0 as input capture. by programming of cap0 to ? 1 ? , the period of signal from int2 can be measured and then, event counter value for int2 can be read. chapter 4. peripheral hardware
4 - 22 concurrence clear interrupt concurrence clear interrupt ift0 t0st t0cn 0 0 1 0 1 counter count stop clear & count stop count continue clear & start fig. 4. 11. start/stop operation of timer0 fig. 4. 12. input capture operation of timer0 t0 t1 t2 t3 int0 chapter 4. peripheral hardware t0 data register value t0 value clear & start
4 - 23 during counting-up, value of counter can be read. timer execution is stopped by the reset signal (reset = ? l ? ) (note) in the process of reading 16-bit timer data, first read the upper 8-bit data. then read the lower 8-bit data, and read the upper 8-bit data again. if the earlier read upper 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. if not, caution should be taken in the selection of upper 8-bit data. example) 1) upper 8-bit read 0a 0a 2) lower 8-bit read ff 01 3) upper 8-bit read 0b 0b ? ? 4.2.3.1 single/modulo-n mode timer0 (timer1) can select initial (t0init, t1init of tm0, tm1) output level of timer output port. if initial level is ? l ? , low-data register value of timer data register is transferred to comparator and t0out(t1out) is to be ? low ? , if initial level is ? high ? , high -data register is transferred and to be ? high ? . single mode can be set by mode select bit(t0mod, t1mod) of timer mode register (tm0, tm1) to ? 1 ? when used as single mode, timer counts up and compares with value of data register. if the result is same, time out interrupt occurs and level of timer output port toggle, then counter stops as reset state. when used as modulo-n mode, t0mod(t1mod) should be set ? 0 ? . counter counts up until the value of data register and occurs time-out interrupt. the level of timer output port toggle and repeats process of counting the value which is selected in data register. during modulo-n mode, if interrupt select bit(t0ifs, t1ifs) of mode register is ? 0 ? , interrupt occurs on every time-out. if it is ? 1 ? , interrupt occurs every second time-out. (*note. timer output is toggled whenever time out happen) 0aff 0b01 chapter 4. peripheral hardware
4 - 24 8bit / 16bit counting 8bit / 16bit counting timer enable initial. value toggle. timer-output toggle. interrupt occurs. count stop. timer enable initial. value toggle. timer-output toggle. int occurs(ifs = 1) each 2nd time out. int occurs(ifs = 0) when time out. < single mode > < modulo-n mode > fig. 4. 13 operation diagram for single/modulo-n mode chapter 4. peripheral hardware
4 - 25 4.2.4 timer2 timer2 operates as a up-counter. the content of t2dr are compared with the contents of up-counter. if a match is found. timer2 interrupt (ift2) is generated and the up-counter is cleared to ? 00h ? . therefore, timer2 executes as a interval timer. interrupt period is determined by the count source clock for the timer2 and content of t2dr. when t2st is set to 1, count value of timer 2 is cleared and starts counting- cup. for clearing and starting the timer2. t2st have to set to ? 1 ? after set to ? 0 ? . in order to write a value directly into the t2dr, t2st should be set to ? 0 ? . count value of timer2 can be read at any time. fig. 4. 14 operation of timer2 concurrence concurrence concurrence clear clear clear 0 t2 data registers value t2 value interrupt interrupt interrupt interval period ift0 chapter 4. peripheral hardware
4 - 26 concurrence clear interrupt concurrence clear interrupt ift2 t2st 0 count stop by 0 count start clear by 1 counter count up count continue count up after clear fig. 4. 15. start/stop of timer2 t2 data register value t2 value count stop chapter 4. peripheral hardware
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
5 - 1 chapter 5. interrupt the gms810 series contains 8 interrupt sources; 3 externals and 5 internals. nested interrupt services with priority control is also possible. software interrupt is non- maskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2ext, 3timer, bit, wdt and key scan) - 8 interrupt vector - nested interrupt control is possible - programmable interrupt mode ? hardware accept mode ? software selection accept mode - read and write of interrupt request flag are possible. - in interrupt accept, request flag is automatically cleared. interrupt hardware consists of interrupt mode register(mod), interrupt enable register high (ienh), interrupt enable register low(ienl), interrupt request register high(irqh), interrupt request register low(irql) and priority circuit. interrupt function block diagram is shown in fig. 5.1 5.1 interrupt source each interrupt vector is independent and has its own priority. software interrupt(brk) is also available. interrupt source classification is shown in table 5.1 chapter 5. interrupt
5 - 2 internal data bus - - - - - - - - - - kscnr int1r int2r t0r t1r t2r wdtr bitr priority control 0 7 0 7 0 7 ienl ienh imod irq kscn int1 int2 ift0 ift1 ift2 ifwdt ifbit int. vector addr. brk standby mode release fig. 5.1 interrupt source hardware interrupt mask non-maskable priority - interrupt source rst (reset pin) int vector h ffff int vector l fffe maskable 0 kscnr (key scan) fffb fffa 1 int1r(external interrupt 1) fff9 fff8 2 int2r(external interrupt 2) fff7 fff6 3 t0r (timer0) fff3 fff2 4 t1r (timer1) fff1 fff0 5 t2r (timer2) ffef ffee 6 wdtr (watch dog timer) ffe9 ffe8 7 bitr (basic interval timer) ffe7 ffe6 table 5.1 interrupt source chapter 5. interrupt - - brk instruction ffdf ffde software interrupt
5 - 3 5.2 interrupt control register i flag of psw is a interrupt mask enable flag. when i flag = ? 0 ? , all interrupts become disable. when i flag = ? 1 ? , interrupts can be selectively enabled and disabled by contents of corresponding interrupt enable register. when interrupt is occured, interrupt request flag is set, and interrupt request is detected at the edge of interrupt signal. the accepted interrupt request flag is automatically cleared during interrupt cycle process. the interrupt request flag maintains ? 1 ? until the interrupt is accepted or is cleared in program. in reset state, interrupt request flag register(irqh, irql) is cleared to ? 0 ? . it is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (refer to software interrupt). - wdtr bite - - - - - ienl r/w <00cch> 7 0 interrupt enable register low kscne int1e int2e - t0e t1e t2e - ienh r/w <00ceh> 7 0 interrupt enable register high - wdtr bite - - - - - irql r/w <00cdh> 7 0 interrupt request register low kscnr int1r int2r - t0r t1r t2r - irqh r/w <00cfh> 7 0 interrupt request register high chapter 5. interrupt
5 - 4 5.3 interrupt accept mode the interrupt priority order is determined by bit(im1, im0) of imod register. - - im1 im0 ip3 ip2 ip1 ip0 imod r/w <00cah> 7 0 interrupt mode register im1 im0 priority 0 0 fixed by h/w 0 1 changeable by ip 3-0 1 * interrupt is inhibited 5.3.1 selection of interrupt by ip3 - ip0 the condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be ? 1 ? . ip3 0 0 0 0 0 0 0 1 1 1 1 1 ip2 0 0 0 1 1 1 1 0 0 0 0 1 ip1 0 1 1 0 0 1 1 0 0 1 1 0 ip0 1 0 1 0 1 0 1 0 1 0 1 0 selection interrupt kscnr (key scan) int1r (external interrupt 1) int2r (external interrupt 2) reserved t0r (timer 0) t1r (timer 1) t2r (timer 2) reserved reserved wdtr (watch dog timer) bitr (basic interval timer) reserved table 5.2 interrupt selection by ip3 - ip0 chapter 5. interrupt assigning by interrupt accept mode bit *in reset state, these ip3 - ip0 registers become all ? 0 ? .
5 - 5 5.3.2 interrupt timing clock sync a command before interrupt interrupt process step interrupt request sampling fig. 5.2 interrupt enable accept timing interrupt request sampling time maximum 12 machine cycle (when execute div instruction) minimum 0 machine cycle interrupt overhead maximum 1 + 12 + 8 = 21 machine cycle minimum 1 + 0 + 8 = 9 machine cycle 5.3.3 the valid timing after executing interrupt control instructions i flag is valid just after executing of ei/di on the contrary. interrupt enable register is valid one instruction after controlling interrupt enable register. interrupt preprocess step is 8 machine cycle chapter 5. interrupt
5 - 6 5.4 interrupt processing sequence when an interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. after the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occured. as soon as an interrupt is accepted, the content of the program counter and psw are saved in the stack area. at the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. in order to execute the interrupt service routine, it is necessary to write the jump addresses in the vector table (ffeoh-ffffh) corresponding to each interrupt interrupt processing step 1) store upper byte of program counter, sp ?? sp 2) store lower byte of program counter, sp ?? sp - 1 3) store program status word, sp ?? sp - 2 4) after resetting of i-flag, clear accepted interrupt request flag.(set b-flag for brk instruction) 5) call interrupt service routine chapter 5. interrupt
5 - 7 clock sync r/w internal addr. bus internal data bus internal read internal write pc sp sp-1 sp-2 lva*2 hva*3 new pc op code op code pch pcl psw ? l ? vector ? h ? vector fig. 5. 3 interrupt procesing step timing *1 isr : interrupt service routine *2 lva : low vector address *3 hva : high vector address 5.1 software interrupt 5.5.1 interrupt by break(brk) instruction software interrupt is available just by writing ? break(brk) ? instruction. the values of pc and psw is stacked by brk instruction and then b flag of psw is set and i flag is reset. n v g b h i z c flag change by brk execution psw n v g 1 h 0 z c psw set reset (right after brk execution) chapter 5. interrupt interrupt process step isr *1
5 - 8 interrupt vector of brk instruction is shared by vector of table call(tcall0). when both instruction of brk and tcall0 are used, as shown in fig. 5.4 each processing routine is judged by contents of b flag. there is no instruction to reset directly b flag. b flag brk interrupt routine tcall0 routine reti ret brk or tcall0 0 1 fig. 5.4 execution of brk or tcall0 5.6 multiple interrupt if there is an interrupt, interrupt mask enable flag is automatically cleared before entering the interrupt service routine. after then, no interrupt is accepted. if ei instruction is executed, interrupt mask enable bit becomes ? 1 ? , and each enable bit can accept interrupt request. when two or more interrupts are generated simultaneously, the highest priority interrupt set by interrupt mode register is accepted. chapter 5. interrupt
5 - 9 5.7 key scan input processing key scan interrupt is generated by detecting low input from each input pin (r0, r1) or standby(sleep, stop) release signal. key scan ports are all 16bit which are controlled by stand-by mode release register (smrr0, smrr1). key input is considered as interrupt, therefore, kscne bit of iehn should be set for correct interrupt executing, sleep mode and stop mode, the rest of executing is the same as that of external interrupt. each smrr register bit is allowed for each port(for bit=0, no key input, for bit=1, key input available). at reset, smrr becomes ? 00h ? . so, there is no key input source. r00 r01 . . r07 r10 r11 . . r17 r0 port selection logic r1 port selection logic smrr0 w <00dch> w <00ddh> smrr1 7 0 7 0 chapter 5. interrupt internal key scan interrupt
5 - 10 smrr0 mode register kr07 kr06 kr05 kr04 kr03 kr02 kr01 kr00 smrr0 w <00dch> 7 0 kr00 key input selection 0 1 no select select kr01 key input selection 0 1 no select select kr02 key input selection 0 1 no select select kr03 key input selection 0 1 no select select kr04 key input selection 0 1 no select select kr05 key input selection 0 1 no select select kr06 key input selection 0 1 no select select kr07 key input selection 0 1 no select select chapter 5. interrupt
5 - 11 smrr1 mode register kr17 kr16 kr15 kr14 kr13 kr12 kr11 kr10 smrr1 w <00ddh> 7 0 kr10 key input selection 0 1 no select select kr11 key input selection 0 1 no select select kr12 key input selection 0 1 no select select kr13 key input selection 0 1 no select select kr14 key input selection 0 1 no select select kr15 key input selection 0 1 no select select kr16 key input selection 0 1 no select select kr17 key input selection 0 1 no select select chapter 5. interrupt
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
6 - 1 chapter 6. standby function to save power consumption, there is stop modes. in this modes, the execution of program stops. 6.1 stop mode stop mode can be entered by stop instruction during program. in stop mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. all registers and ram data are preserved. ? nop ? instruction should be follows stop instruction for rising precharge time of data bus line. ex) stop : stop instructiion excution nop : nop instruction chapter6. standby function
6 - 2 selector prescaler enpck basic interval timer ps10 peripheral fig. 6.2 enpck and basic interval timer clock fig. 6.1 block diagram of standby circuit chapter6. standby function osc. circuit clock pulse gen clr mux prescaler clr s q r s q r overflow detection basic interval timer clr cpu clock b.i.t 7 stop release signal from interrupt circuit reset control signal
6 - 3 6.2 standby mode release 6.2.1 stop mode release release of standby mode is executed by reset input and interrupt signal. register value is defined when reset. when there is a release signal of stop mode (interrupt, reset input), the instruction execution starts after stabilization oscillation time is set by value of bts2~bts0 and set enpck to 1. table 6.1. standby mode register release signal stop reset 0 kscn (key input) 0 int1 - int2 0 table 6.2 standby mode release release factor release method reset pin by reset pin = low level, standby mode is release and system is initialized kscn (key input) standby mode is released by low input of selected pin by key scan input (smrr0, smrr1) in case of interrupt mask enable flag = 0, program executes just after standby instruction, if flag = 1, enters each interrupt service routine. int 1 pin int 2 pin when external interrupt (int1, int2) enable flag is ? 1 ? , standby mode is released at the rising edge of each terminal. when standby mode is released at interrupt. mask enable flag = 0, program executes from the next instruction of standby instruction. when 1, enters each interrupt service routine. chapter6. standby function
6 - 4 stop mode stable osc. time program setting time by ckctlr refer to table 4-1 longer than stable osc. time clcok release by interrupt reset fig. 6.3 release timing of standby mode 6.3 release operation of standby mode after standby mode is released, the operation begins according to content of related interrupt register just before standby mode start(fig. 6.3) 6.3.1 in case of interrupt enable flag(i) of psw = 0 release by only interrupt which interrupt enable flag = 1, and starts to execute from next to standby instruction (stop). chapter6. standby function
6 - 5 6.3.2 in case of interrupt enable flag(i) of psw = 1 released by only interrupt which each interrupt enable flag = 1, and jump to the relevant interrupt service routine. note) when stop instruction is used, b.i.t should guarantee the stabilization oscillation time. thus, just before entering stop mode, clock of bit10(ps10) of prescaler is selected or peripheral hardware clock control bit(enpck) to 1, therefore the clock necessary for stabilization oscillation time should be input into b.i.t. otherwise, standby mode is released by reset signal. in case of interrupt request flag and interrupt enable flag are both ? 1 ? , standby mode is not entered. fig. 6.5 standby mode release flow stop command standby mode interrupt request gen. ie flag standby mode release psw ie flag interrupt service routine standby next command execution 0 1 0 1 chapter6. standby function
6 - 6 internal circuit stop mode oscillator stop internal cpu clock stop register retained ram retained i/o port retained prescaler stop basic interval timer stop watch dog timer stop timer stop address bus, data bus retained table 6.3 operation state in standby mode chapter6. standby function
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
7 - 1 chapter 7. reset function 7.1 external reset the reset pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uf capacitor for stable system initialization. the reset pin contains a schmitt trigger with an internal pull-up resistor. 0.1uf capacitor fig 7.0 reset pin connection. 7.2 power on reset power on reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, reset terminal is maintained at ? l ? level until a crystal ceramic oscillator oscillates stably. after power applies and starting of oscillation, this reset state is maintained for about oscillation cycle of 2 19 (about 65.5ms : at 4mhz). the execution of built-in power on reset circuit is as follows : (1) latch the pulse from power on detection pulse generator circuit, and reset prescaler, b.i.t and b.i.t overflow detection circuit. (2) once b.i.t overflow detection circuit is reset. then, prescaler starts to count. (3) prescaler output is inputted into b.i.t and ps10 of prescaler output is automatically selected. if overflow of b.i.t is detected, overflow detection circuit is set. (4) reset circuit generates maximum period of reset pulse from prescaler and b.i.t. chapter7. reset function reset
7 - 2 fig. 7.1 block diagram of power on reset circuit notice ; when power on reset, oscillator stabilization time doesn`t include osc. start time. fig. 7.2 oscillator stabilization diagram reset power on det pulse gen. osc. clr prescaler clr basic interval tiemr clr basic interval tiemr xtal ps10 msb internal reset chapter7. reset function vdd osc. start timing prescaler count start vdd vss 0.1uf internal ic
7 - 3 reset addr. bus internal data bus sp sp-1 sp-2 fffe ffff new pc fe lsb vector msb vector fig. 7.3 reset timing by diagram chapter7. reset function internal reset
7 - 4 7.3 low voltage detection mode 7.3.1 low voltage detection condition an on board voltage comparator checks that v dd is at the required level to ensure correct operation of the device. if v dd is below a certain level, low voltage detector forces the device into low voltage detection mode. 7.3.2 low voltage detection mode there is no power consumption except stop current, stop mode release function is disabled. all i/o port is configured as input mode and data memory is retained until voltage through external capacitor is worn out. in this mode, all port can be selected with pull-up resistor by mask option. if there is no information on the mask option sheet ,the default pull up option (all port connect to pull-up resistor ) is selected. 7.3.3 release of low voltage detection mode reset signal result from new battery(normally 3v) wakes the low voltage detection mode and come into normal reset state. it depends on user whether to execute ram clear routine or not. chapter7. reset function 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? temperature(?) low voltage (v) 2.6 2.8 3.0 fig 7.5 low voltage vs temperature
7 - 5 chapter7. reset function * sram back-up after low voltage detection. 3.0v 1.8v(typ) ( 20 ?) * sram data backup user removes batteries user replace batteries interrupt : disable stop release : disable all i/o port : input mode remout port : low level osc : stop all i/o port pull-up on (mask option ) sram data retention * the operation after low voltage detection about hours depend on vcc-gnd capacitor 0v low voltage detection point mcu opr. voltage power on reset ( sram unstable ) power on reset ( sram retention) 0.7v(v ret ) * s/w flow chart example after reset using sram back-up reset stack pointer initialize sram data is valid? check the sram value (ram pattern, check sum..) n y clear all ram area use saved sram value
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
a - 1 appendix a. instruction set table appendix a. instruction set table no. mnemonic op code words exec. cycle operation flag mvg hizc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 adc #imm adc dp adc dp+x adc !abs adc !abs+y adc [dp+x] adc [dp]+y adc {x} and #imm and dp and dp+x and !abs and !abs+y and [dp+x] and [dp]+y and {x} asl a asl dp asl dp+x asl !abs bbc a.bit, rel bbc dp.bit, rel bbs a.bit, rel bbs dp.bit, rel bcc rel bcs rel beq rel bit dp bit !abs bmi rel bne rel bpl rel bra rel brk bvc rel bvs rel clr1 dp.bit clra1 a.bit clrc clrg clrv 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 y2 y3 x2 x3 50 d0 f0 0c 1c 90 70 10 2f 0f 30 b0 y1 2b 20 40 80 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 3 2 3 2 2 2 2 3 2 2 2 2 1 2 2 2 2 1 1 1 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 4/6 5/7 4/6 5/7 2/4 2/4 2/4 4 5 2/4 2/4 2/4 4 8 2/4 2/4 4 2 2 2 2 a = a + op + c ? ? ? ? ? ? ? a = a & op ? ? ? ? ? ? ? op = op << 1 ? ? ? if (bit = 0) then branch if (bit = 1) then branch if (c=0) branch if (c=1) branch if (z=1) branch z = a & op ? if (n=1) branch if (z=0) branch if (n=0) branch branch s/w interrupt if (v=0) branch if (v=1) branch op.bit = 0 ? c = 0 g = 0 v = 0 n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n n . . . . z . n n . . . . z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 . . 0 . . . . . . 0 . . 0 . . .
a - 2 no. mnemonic op code words exec. cycle operation flag mvg hizc 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 cmp #imm cmp dp cmp dp+x cmp !abs cmp !abs+y cmp [dp+x] cmp [dp]+y cmp {x} com dp cmpx #imm cmpx dp cmpx !abs cmpy #imm cmpy dp cmpy !abs daa das dec a dec dp dec dp + x dec !abs dec x dec y div di ei eor #imm eor dp eor dp+x eor !abs eor !abs+y eor [dp+x] eor [dp]+y eor {x} inc a inc dp inc dp + x inc !abs inc x inc y jmp !abs jmp [!abs] jmp [dp] call !abs call [dp] pcall upage tcall n 44 45 46 47 55 56 57 54 2c 5e 6c 7c 7e 8c 9c df cf a8 a9 b9 b8 af be 9b 60 e0 a4 a5 a6 a7 b5 b6 b7 b4 88 89 99 98 8f 9e 1b 1f 3f 3b 5f 4f na 2 2 2 3 3 2 2 1 2 2 2 3 2 2 3 1 1 1 2 2 3 1 1 1 1 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 3 3 2 3 2 2 1 2 3 4 4 5 6 6 3 4 2 3 4 2 3 4 3 3 2 4 5 5 2 2 12 3 3 2 3 4 4 5 6 6 3 2 4 5 5 2 2 3 5 4 8 8 6 8 compare a, op ? ? ? ? ? ? ? dp = dp compare x, op ? ? compare y, op ? ? ? dec. adjustment (add) dec. adjustment (sub) op = op -1 ? ? ? ? ? q:a, r:y ?? ya/x i = 0 i = 1 a = a + op ? ? ? ? ? ? ? op = op + 1 ? ? ? ? ? branch ? ? subroutine call ? ? ? n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z . n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n v . . h . z . . . . . . 0 . . . . . . . 1 . . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a. instruction set table
a - 3 no. mnemonic op code words exec. cycle operation flag mvg hizc 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 lda #imm lda dp lda dp+x lda !abs lda !abs+y lda [dp+x] lda [dp]+y lda {x} lda {x}+ ldm dp, #imm ldx #imm ldx dp ldx dp+y ldx !abs ldy #imm ldy dp ldy dp+x ldy !abs lsr a lsr dp lsr dp + x lsr !abs mul nop or #imm or dp or dp+x or !abs or !abs+y or [dp+x] or [dp]+y or {x} push a push x push y push psw pop a pop x pop y pop psw rol a rol dp rol dp+x rol !abs ror a ror dp ror dp+x ror !abs c4 c5 c6 c7 d5 d6 d7 d4 db e4 1e cc cd dc 3e c9 d9 d8 48 49 59 58 5b ff 64 65 66 67 75 76 77 74 0e 2e 4e 6e 0d 2d 4d 6d 28 29 39 38 68 69 79 78 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 1 2 2 3 1 1 2 2 2 3 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 3 1 2 2 3 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 2 4 5 5 9 2 2 3 4 4 5 6 6 3 4 4 4 4 4 4 4 4 2 4 5 5 2 4 5 5 a = op ? ? ? ? ? ? ? a = op, x = x+1 dp = #imm x = op ? ? ? y = op ? ? ? op = op >>1 ? ? ? ya = y * a no operation a = a : op ? ? ? ? ? ? ? push op, sp = sp - 1 ? ? ? pop op, sp = sp + 1 ? ? ? op = op << 1, with c ? ? ? op = op >> 1, with c ? ? ? n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . . . . . . . . . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z . . . . . . . . . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (restored) n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c n . . . . . z c appendix a. instruction set table
a - 4 no. mnemonic op code words exec. cycle operation flag mvg hizc 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 reti ret sbc #imm sbc dp sbc dp+x sbc !abs sbc !abs+y sbc [dp+x] sbc [dp]+y sbc {x} seti dp.bit seta1 a.bit setc setg sta dp sta dp+x sta !abs sta !abs+y sta [dp+x] sta [dp]+y sta {x} sta {x}+ stop stx dp stx dp+y stx !abs sty dp sty dp+x sty !abs tax tay tst dp tspx txa txsp tya xax xay xcn xma dp xma dp+x xma {x} xyx 7f 6f 24 25 26 27 35 36 37 34 x1 0b a0 c0 e5 e6 e7 f5 f6 f7 f4 fb ef ec ed fc e9 f9 f8 e8 9f 4c ae c8 8e bf ee de ce bc ad bb fe 1 1 2 2 2 3 3 2 2 1 2 2 1 1 2 2 3 3 2 2 1 1 1 2 2 3 2 2 3 1 1 2 1 1 1 1 1 1 1 2 2 1 1 6 5 2 3 4 4 5 6 6 3 4 2 2 2 4 5 5 6 7 7 4 4 3 4 5 5 4 5 5 2 2 3 2 2 2 2 4 4 5 5 6 5 4 interrupt end subroutine end a = a - op - c ? ? ? ? ? ? ? op.bit = 1 ? c = 1 g = 1 op = a ? ? ? ? ? ? op = a, x=x+1 cpu, osc stop op = x ? ? op = y ? ? x= a y = a test dp = 0 or not x = sp a = x sp = x a = y a ? x a ? y a7-4 a3-0 a ? op ? ? x ? y (restored) . . . . . . . . n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c n v . . h . z c . . . . . . . . . . . . . . . . . . . . . . . 1 . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . . . . . . . . . n . . . . . z . . . . . . . . . . . . . . . . . n . . . . . z . n . . . . . z . n . . . . . z . n . . . . . z . . . . . . . . appendix a. instruction set table
a - 5 no. mnemonic op code words exec. cycle operation flag mvg hizc 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 ldya dp stya dp incw dp decw dp addw dp subw dp cmpw dp cbne dp, rel cbne dp+x, rel dbne dp, rel dbne y, rel not1 m.bit or1 m.bit or1b m.bit and1 m.bit and1b m.bit eor1 m.bit eor1b m.bit ldc m.bit ldcb m.bit stc m.bit tclr1 !abs tset1 !abs 7d dd 9d bd 1d 3d 5d fd 8d ac 7b 4b 6b 6b 8b 8b ab ab cb cb eb 5c 3c 2 2 2 2 2 2 2 3 3 3 2 3 3 3 3 3 3 3 3 3 3 3 3 5 5 6 6 5 5 4 5/7 6/8 5/7 4/6 5 5 5 4 4 5 5 4 4 6 6 6 ya = (dp+1)(dp) (dp+1)(dp) = ya (dp+1)(dp)++ (dp+1)(dp)-- ya + (dp+1)(dp) ya - (dp+1)(dp) cp ya, (dp+1)(dp) if (op !=a) then branch dec op, if (z=0) then branch m.bit = m.bit c = m.bit : c c = (m.bit) : c c = m.bit & c c = (m.bit) & c c= m.bit + c c = (m.bit) + c c = m.bit c = (m.bit) m.bit = c !abs = a & !abs !abs = a : !abs n . . . . . z . . . . . . . . . n . . . . . z . n . . . . . z . n v . . h . z c n v . . h . z c n . . . . . z c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . c . . . . . . . . n . . . . . z . n . . . . . z . appendix a. instruction set table
overview 1 function description 2 i/o port 3 peripheral hardware 4 interrupt 5 standby function 6 reset function 7 appendix a. 8 appendix b. 9
b - 1 appendix b. programmer`s guide appendix b. general circuit diagram of gms810series. key matrix = key 17 9 1 18 10 2 19 11 3 20 12 4 21 13 5 22 14 6 23 15 7 24 16 8 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 r15 r14 r13 r12 r11 r10 r00 r01 r02 r03 r04 r05 r06 r07 49 50 51 52 53 54 55 56 r16 osc r13 r14 r12 r15 r11 r16 r10 r17 vdd remout xout reset xin test r00 r07 r01 r06 r02 r05 r03 r04 r20 vss tr1 gms 81016 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 vcc gnd 14 13 11 12 0.1uf 220uf 0.1uf dc3v indicator led vcc vcc b-1 circuit diagram vcc infrared led 4mhz normally use the above 100uf capacitor for prevent power drop during pulse is transmitted. if you use the sram back-up, use at least 220uf we recommend to use alkaline battery. filter for vcc-gnd noise
b - 2 gms810 mask option list hyundai elctronics co., ltd. m c u application team. code name : gms81016 - uaxxx 1. device & package please enter check marks as 2. inclusion of pull up resistor - r1 port y : yes n : no - r2 port date : company name : section name : signature : 24pin : sop skinny dip 28pin : sop skinny dip y : yes n : n o - r0 port y : yes n : no 20pin : sop pdip < notice > . *0 : is only available in low voltage detection option = y (no . 3) *1 : is not available for 20pin & 24pin. so, default option is pull-up. . *2 : is not available for 20pin. so, default option is pull-up. gms81008 gms81016 gms81004 gms81032 GMS81024 44pin : plcc 3. low voltage detection y/n n port r00 y/n y y/n *0 r01 y r02 y r03 y r04 y r05 y r06 y r07 y port r10 y/n n y/n *0 r11 n r12*2 n r13*2 n r14*2 n r15*2 n r16 n r17 n port r20 y/n n y/n *0 r21*1 r22*1 r23*1 r24*1 mask option list example refer to circuit b-1 b-1 ,circuit description: device : gms81016 package : 24pin sop port r0x : all input port with pull-up resistor port r1x : all output port with n-mos open drain port r20 : led drive port ; example program for port setting. org 0c000h ; gms81016 program start address reset : clrg ; clear g-flag ldx #0feh ; stack pointer initialize txsp di ; interrupt disable ldm r2dd,#0001_1111 b ; r2 direction setting,r20: output ldm r2,#1111_1111b ; r2 data setting , r20 : high,led off ldm r1odc,#1111_1111b ; r1 port all open drain ldm r1dd,#1111_1111b ; r1 direction setting ,all output ldm r1,#0000_0000b ; r1 data setting , all low for key scan ldm r0dd,#0000_0000b ; r0 direction setting ,all input ldm smrr0,#1111_1111b ; stop mode release by r0 ldm smrr1,#0000_0000b ; stop disable by r1 ldm ienh,#1000_0000b ; key scan interrupt setting ldm ckctlr,#0001_1101b ; ckctlr setting for 16ms time delay after ; release from stop mode, wdt disable. clr1 irqkscn ; key scan interrupt request flag clear stop nop ; `nop instruction must to be used after ldm r1,#1111_1111b ; stop instruction s/w example refer to circuit b-1 appendix b. programmer`s guide
b - 3 appendix b. programmer`s guide key scan - to secure the key board scanning , read the input port after minimum 60us delay time from output port set to `low `. this time delay is for the port rising time depend on the input pull-up resistor . ; program example ,see the circuit b-1 . ldm r1,#1111_1110b ;r10 port set to low call delay_60us ;60us time delay routine lda r0 ;r0 port read . . r10 r11 60us 60us r0 port read timing fig b-2 , input with pull-up port read time method
gms810 mask option list hyundai electronics co., ltd. mcu application team. code name : 1. device & package please enter check marks as 2. inclusion of pull up resistor - r1 port y : yes n : no - r2 port date : company name : section name : signature : 24pin : sop skinny dip 28pin : sop skinny dip y : yes n : no - r0 port y : yes n : no 20pin : sop pdip < notice > . *0 : is only available in . low voltage detection option = y ( no. 3 ) *1 : is not available for 20pin & 24pin. so, default option is pull-up. . *2 : is not available for 20pin. so default option is pull-up. gms81008 gms81016 gms81004 gms81032 GMS81024 44pin : plcc 3. low voltage detection r04 r05 r06 r07 port r00 r01 r02 r03 y/n y/n r14 r15 r16 r17 port r10 r11 r12 r13 y/n y/n *2 *2 *2 *2 r24 port r20 r21 r22 r23 y/n y/n *1 *1 *1 *1 y/n *0 *0 *0
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